1. Field of the Invention
The present invention relates to an image producing apparatus having an image memory which is to develop and output bit map data.
2. Description of the Related Art
A conventional image producing apparatus will be described by making reference to an example of a laser printer which is a generally used one of image producing apparatuses. FIG. 7 is a block diagram of a conventional laser printer. As shown there, the laser printer is constructed with five blocks including: interface means 2; video data processing means 3; a laser scan unit section 4 (hereinafter abbreviated as an LSU section); engine control means 5; and an engine mechanical section 6.
The outline of the laser printer having the above construction will be described hereinbelow. The laser printer connected with a host computer 1 receives text data sent from the host computer 1 through the interface means 2 and stores it in the memory in the video data processing means 3. Then, the text data is developed in the form of a bit map data used as an image data in the video data processing means 3, and the resultant data is sent to the LSU section as a serial output video data (hereinafter, abbreviated as VDOUT) is synchronism with a horizontal sync signal (hereinafter, abbreviated as HSYNC) supplied from the LSU section 4 operating as an output apparatus. At the same time, along with the outputting of the VDOUT, the video data processing means 3 manages an engine control means 5 for controlling the operations of an engine mechanical section 6 including paper feed, main motor drive, and the like. As mentioned above, the image formation of image data is effected.
With respect to the laser printer constructed as mentioned above, FIG. 8 is a block diagram of a video data processing section showing a conventional construction of the video data processing means 3. In the diagram, reference numeral 7 denotes an MPU; 8 indicates a DRAM block section having a DRAM; and 9 represents a VRAM block section. Reference numeral 10 denotes address decoding means which uses an address bus (MPUA) of the MPU 7 as an input thereto, performs decoding of addresses, and discriminates to which one of the memories of the DRAM block section 8 and the VRAM block section 9 the MPU 7 requests its access. Then, the address decoding means 10 generates and supplies an access request signal (DRAMRQ) for requesting an access to the DRAM block section 8 to DRAM arbitration means 12, which will be explained later, or an access request signal (VRAMRQ) for requesting an access to the VRAM block section 9 to VRAM arbitration means 16, which will also be explained later. Reference numerals 11 and 15 denote refreshing means for the DRAM block section 8 and the VRAM block section 9, respectively, and they are means for requesting the refreshment of the DRAM block section 8 and the VRAM block section 9, respectively. The refreshing means 11 generates and supplies a refresh request signal (DREFRQ) to the DRAM arbitration means 12, and the refreshing means 15 generates and supplies a refresh request signal (VREFRQ) to the VRAM arbitration means 16. Reference numerals 12 and 16 denote respective arbitration means for the DRAM block section 8 and the VRAM block section 9, respectively. The DRAM arbitration means 12 arbitrates the access request signal DRAMRQ and the refresh request signal DREFRQ and outputs a DRAM start command signal group (DSTCOM), that indicates a state showing which arbitration has resulted, to DRAM timing means 13 which will be explained later. The VRAM arbitration means 16 arbitrates the access request signal VRAMRQ and the refresh request signal VREFRQ and outputs a VRAM start command signal group (VSTCOM), that indicates a state showing which arbitration has resulted, to VRAM timing means 17 which will be explained later. Reference numeral 14 indicates bank switching means which inputs the address bus MPUA and sends a bank switching state signal group (BANKST) to the DRAM timing means 13, which will be explained later.
Since the user's area for storing the text data in the DRAM block section 8 is fixed and limited, it is necessary to expand the memory capacity in accordance with an amount of user's text data in order to prevent occurrence of memory overflow. Thus bank switching is executed when the memory of the DRAM block section 8 is expanded. Reference numeral 13 denotes DRAM timing means which generates a timing signal group (DRAMT) for making DRAM access to the DRAM block section 8 by the signal group DSTCOM, which are sent from the DRAM arbitration means 12, and, at the same time, which receives the signal group BANKST sent from the bank switching means 14 and supplies a bank information signal (BANK0) to the DRAM block section 8. Although FIG. 8 does not show this, it is assumed that there are provided expansion DRAM block sections for bank information signals BANK1 and BANK2 in the same way as the DRAM block section 8 for the bank information signal BANK0. As mentioned above, the address bus MPUA, the bank information signal BANK0, the timing signal group DRAMT, and a data bus MPUD are connected with the DRAM block section 8, thereby enabling access of the MPU 7 to the DRAM. Reference numeral 17 denotes the VRAM timing means for receiving the signal group VSTCOM sent from the VRAM arbitration means 16 and for sending a timing signal group (VRAMT) for the VRAM access to the VRAM block section 9. The VRAM block section 9 is connected to the address bus MPUA and the data bus MPUD and receives the timing signal group (VRAMT) and sends the video data, which is a serial output, to video signal synchronizing means 18, which will be explained later, in accordance with clocks which are sent from the video signal synchronizing means 18 via video data bus (VDB). As mentioned above, the video data bus VDB is constructed by the clock line and the serial data line. Since the capacity of the memory buffer of the VRAM block section 9 is generally limited, there occurs a state of error (hereinafter, such a state of error is referred to as an overrun) in which the data, which has not yet been subjected to image data development, is transferred, when the sequential reading speed of the sync signal HSYNC is faster than the developing speed of the image data into the memory buffer. In order to expand the overrun-free range, it is necessary to increase the capacity of the memory buffer in the VRAM block section 9. Reference numeral 18 denotes the video signal synchronizing means for counting the blanking time and generating clocks for the VRAM block section 9 so as to output the video data sent from the VRAM block section 9 to an effective printing area in synchronism with a sync signal HSYNC sent from the LSU section 4 (not shown), and sending the generated clocks as a serial video data output VDOUT to the LSU. On the other hand, the MPU 7 detects the sync signal HSYNC and counts the number of rasters of the output data, and also performs the control and management of the VRAM block section 9 and the video signal synchronizing means 18.
As mentioned above, the memories are separated to be independent of each other so that the system and the user's area are assigned to the DRAM block section 8 and the image data is developed in the VRAM block section 9. Since the VRAM block section 9 is constructed to have dual ports, the access by the MPU 7 and the access by the clocks from the video signal synchronizing means 18 can be easily performed.
On the contrary, there have been inconveniences such that expansion boards for expanding the memory area are independently needed for the DRAM block section 8 and the VRAM block section 9. The utilization facility of such a construction has been degraded for the user. In this art field, a high resolution display using bit-mapped data is known as a bit map display system. In the conventional bit map display system, each picture element (pixel) corresponds to data bits stored in a memory; usually, data to be displayed is stored in a predetermined memory area (termed a frame buffer) of the memory in the form of a directly displayable pattern. This display pattern is termed a "bit map". Hereinafter, the term "bit-developing" will be used in conjunction with the improved and novel image processing system of the present invention.
FIG. 9 shows characters which have been developed as bit map data to form image data of an image. For instance, an explanation will be made of the development of characters A and B. For convenience of explanation, it is assumed that each character is constructed by 25.times.25 dots, one dot is in one bit unit, one dot painted in black corresponds to 1, and one blank dot to 0. Each bit information of 25.times.25 dots is stored in a character font using a code of 1 or 0. The text data stored in the DRAM is developed as bit map data in the buffer of the VRAM by making reference to the character font via the MPU. Generally, in the above development, characters are sequentially developed one by one and written in the buffer. In FIG. 9, the character "A" is first developed as a bit map in the buffer of the VRAM, and each bit is written in accordance with the code of the character font. Then, the bit map development of the character "B" is made. In the case where the characters "A" and "B" are overlaid, if the ordinary writing operation is performed, the 25.times.25 bits are written by the information of the character "B" at the time point when the writing operation of the character "B" is performed, so that the character "A" is partially erased. To prevent it, after the character "A" has been developed, the OR operation of the characters "A" and "B" is performed on a bit unit basis so that the overlaid information is written in the buffer, whereby an overlaid character as shown in FIG. 9 can be written. Such a function is hereinafter referred to as an overlaid-writing. Generally, the VRAM has the overlaid-writing function, and it is assumed that the VRAM, which is referred to hereinlater, has such a function.
The control which is executed by the MPU 7 in FIG. 8 will now be described by using a flowchart of FIG. 10. With respect to the HSYNC interruption routine, an interruption occurs in the processing of the MPU 7 each time a pulse is applied to the HSYNC input in FIG. 8. An explanation will be made hereinbelow with reference to the flowchart. First, in the main routine, variables X and Y are initialized in step (a). X denotes a raster number which is written in the VRAM area by the MPU 7. Y indicates a counter number indicative of the number of interruption times for every HSYNC. A raster number N to be printed is set in step (b). The HSYNC interruption is permitted in step (c). In step (d), a blanking time and the like are set into the video signal synchronizing means 18 and the means 18 is activated. Instep (e), the magnitudes of X and Y are compared with each other to discriminate whether there exists or not an empty raster by which the bit map data can be written in the VRAM block section 9. If no empty raster exists, the processing routine is returned to the entrance of step (e). If an empty raster exists, the processing proceeds to step (f). In step (f), the bit map data is written in the VRAM block section 9 to the amount of one raster and +1 is added to the value of X. In step (g), a check is made to see if the HSYNC counter number Y is equal or not to the raster number N to be printed. If Y=N, the processing proceeds to step (h). In step (h), the video signal synchronizing means 18 is stopped and the writing of the bit map data in the VRAM block section 9 is completed. Then, in the HSYNC interruption routine, +1 is added to the value of the output raster number Y in step (i). In step (j), Y and N are compared with each other to discriminate whether the printing has been completed or not. If Y=N, the processing proceeds to step (k). If Y.noteq.N, the processing is completed. In step (k), the interruption of HSYNC is inhibited.